Design of a simplified AES Encryption/Decryption Engine using SystemC
The goal of this exercise is to design the behavior of the different hardware blocks that make a AES encryption/decryption system. The following diagram shows the different blocks and their interaction:
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The block diagram above shows the following blocks:
·The IO Interface block: implements the input/output functionality developed in Assignment 3. It uses HDLC protocol to carry packets. Packets are of the following types: (Figures below show the packet formats)
oCtrl packets: used to specify the association of a specified flow with a set of parameters:
§Operation: Either cipher (encryption) or decipher (decryption)
§Mode: Feedback mode: use only two modes: CBC and OFB modes
§Initialization Vector: 128-bits vector used in the feedback modes.
§Key: the used key by specifying its address
§FlowID: the flow ID number with which all the above parameters are associated. We consider a total of 16 different flows
oData Packets: contain the data to be ciphered. Specifies the following parameters:
§FlowID: that will help determine the different parameters with which the data will be processed.
§Number of 128-bits blocks: Number of 128-bits blocks to be processed sequentially. Maximum number is 16 blocks
§Continuity: is the current stream of blocks a continuation of the previous stream and should be chained with them or not?
·The Ctrl block: responsible for:
oStoring the Keys in the Key Memory block
oSaving the parameters associated with the FlowID
oRetrieving the parameters of a given FlowID
·The Key Memory block: stores the different keys in specified locations by the user. The size of the memory is 256 locations to accept 256 Keys of 128-bits length.
·The Key Schedule Generator block: Generates the key schedule according to the AES algorithm requirements and sends it to the Row Scheduler which sends it to the concerned AES Engine Key Schedule Memory.
·The Row Scheduler block: responsible for mapping the cipher/decipher jobs onto the AES Engines. Each Row Scheduler has 12 AES Engines attached to it.
·The AES Engine blocks: Perform encryption/decryption jobs according to the parameters specified for each block.
·The Key Schedule Memory blocks contain the Key Schedules used by the AES Engines. The size of these memories is large to accommodate 8 sets of Key Schedules
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1.Write a SystemC module that describes every single block
2.Connect the different modules and make a testbench to test the different modules.

In this work it is assumed that the entity generating the packets received by this block does not produce errors like two valid sop_in that follow each other without any eop_in in between them. This assumption avoids treating corner cases like this.

Deliverables:
The following items should be delivered:

• SystemC modules containing the design of the blocks
  • SystemC header files (.h)
  • SystemC implementation files (.cpp)
• SystemC testbench containing the stimulus generators as well as instantiating the design module.
• A document file containing the detailed description of the test scenario(s)
• SystemC main file

Waveform files (.vdc) showing two packets received and transformed into HDLC and transmitted out. These packets should have IDLE characters in between each